GPU: Partially implemented the QUERY_* registers in the Maxwell3D engine.

Only QueryMode::Write is supported at the moment.

src/core/CMakeLists.txt

@@ -92,6 +92,8 @@ add_library(core STATIC
     hle/service/aoc/aoc_u.h
     hle/service/apm/apm.cpp
     hle/service/apm/apm.h
+    hle/service/apm/interface.cpp
+    hle/service/apm/interface.h
     hle/service/audio/audio.cpp
     hle/service/audio/audio.h
     hle/service/audio/audin_u.cpp
@@ -137,8 +139,6 @@ add_library(core STATIC
     hle/service/nvdrv/devices/nvmap.h
     hle/service/nvdrv/interface.cpp
     hle/service/nvdrv/interface.h
-    hle/service/nvdrv/memory_manager.cpp
-    hle/service/nvdrv/memory_manager.h
     hle/service/nvdrv/nvdrv.cpp
     hle/service/nvdrv/nvdrv.h
     hle/service/nvdrv/nvmemp.cpp

src/core/core.cpp

@@ -154,6 +154,8 @@ System::ResultStatus System::Init(EmuWindow* emu_window, u32 system_mode) {
         break;
     }
 
+    gpu_core = std::make_unique<Tegra::GPU>();
+
     telemetry_session = std::make_unique<Core::TelemetrySession>();
 
     CoreTiming::Init();

src/core/core.h

@@ -11,6 +11,7 @@
 #include "core/memory.h"
 #include "core/perf_stats.h"
 #include "core/telemetry_session.h"
+#include "video_core/gpu.h"
 
 class EmuWindow;
 class ARM_Interface;
@@ -102,6 +103,10 @@ public:
         return *cpu_core;
     }
 
+    Tegra::GPU& GPU() {
+        return *gpu_core;
+    }
+
     PerfStats perf_stats;
     FrameLimiter frame_limiter;
 
@@ -138,6 +143,8 @@ private:
     ///< ARM11 CPU core
     std::unique_ptr<ARM_Interface> cpu_core;
 
+    std::unique_ptr<Tegra::GPU> gpu_core;
+
     /// When true, signals that a reschedule should happen
     bool reschedule_pending{};
 

src/core/hle/service/apm/apm.cpp

@@ -5,63 +5,15 @@
 #include "common/logging/log.h"
 #include "core/hle/ipc_helpers.h"
 #include "core/hle/service/apm/apm.h"
+#include "core/hle/service/apm/interface.h"
 
 namespace Service {
 namespace APM {
 
 void InstallInterfaces(SM::ServiceManager& service_manager) {
-    std::make_shared<APM>()->InstallAsService(service_manager);
-}
-
-class ISession final : public ServiceFramework<ISession> {
-public:
-    ISession() : ServiceFramework("ISession") {
-        static const FunctionInfo functions[] = {
-            {0, &ISession::SetPerformanceConfiguration, "SetPerformanceConfiguration"},
-            {1, &ISession::GetPerformanceConfiguration, "GetPerformanceConfiguration"},
-        };
-        RegisterHandlers(functions);
-    }
-
-private:
-    void SetPerformanceConfiguration(Kernel::HLERequestContext& ctx) {
-        IPC::RequestParser rp{ctx};
-
-        auto mode = static_cast<PerformanceMode>(rp.Pop<u32>());
-        u32 config = rp.Pop<u32>();
-
-        IPC::ResponseBuilder rb{ctx, 2};
-        rb.Push(RESULT_SUCCESS);
-
-        LOG_WARNING(Service_APM, "(STUBBED) called mode=%u config=%u", static_cast<u32>(mode),
-                    config);
-    }
-
-    void GetPerformanceConfiguration(Kernel::HLERequestContext& ctx) {
-        IPC::RequestParser rp{ctx};
-
-        auto mode = static_cast<PerformanceMode>(rp.Pop<u32>());
-
-        IPC::ResponseBuilder rb{ctx, 3};
-        rb.Push(RESULT_SUCCESS);
-        rb.Push<u32>(0); // Performance configuration
-
-        LOG_WARNING(Service_APM, "(STUBBED) called mode=%u", static_cast<u32>(mode));
-    }
-};
-
-APM::APM() : ServiceFramework("apm") {
-    static const FunctionInfo functions[] = {
-        {0x00000000, &APM::OpenSession, "OpenSession"},
-        {0x00000001, nullptr, "GetPerformanceMode"},
-    };
-    RegisterHandlers(functions);
-}
-
-void APM::OpenSession(Kernel::HLERequestContext& ctx) {
-    IPC::ResponseBuilder rb{ctx, 2, 0, 1};
-    rb.Push(RESULT_SUCCESS);
-    rb.PushIpcInterface<ISession>();
+    auto module_ = std::make_shared<Module>();
+    std::make_shared<APM>(module_, "apm")->InstallAsService(service_manager);
+    std::make_shared<APM>(module_, "apm:p")->InstallAsService(service_manager);
 }
 
 } // namespace APM

src/core/hle/service/apm/apm.h

@@ -14,13 +14,10 @@ enum class PerformanceMode : u8 {
     Docked = 1,
 };
 
-class APM final : public ServiceFramework<APM> {
+class Module final {
 public:
-    APM();
-    ~APM() = default;
-
-private:
-    void OpenSession(Kernel::HLERequestContext& ctx);
+    Module() = default;
+    ~Module() = default;
 };
 
 /// Registers all AM services with the specified service manager.

src/core/hle/service/apm/interface.cpp

@@ -0,0 +1,66 @@
+// Copyright 2018 yuzu emulator team
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/logging/log.h"
+#include "core/hle/ipc_helpers.h"
+#include "core/hle/service/apm/apm.h"
+#include "core/hle/service/apm/interface.h"
+
+namespace Service {
+namespace APM {
+
+class ISession final : public ServiceFramework<ISession> {
+public:
+    ISession() : ServiceFramework("ISession") {
+        static const FunctionInfo functions[] = {
+            {0, &ISession::SetPerformanceConfiguration, "SetPerformanceConfiguration"},
+            {1, &ISession::GetPerformanceConfiguration, "GetPerformanceConfiguration"},
+        };
+        RegisterHandlers(functions);
+    }
+
+private:
+    void SetPerformanceConfiguration(Kernel::HLERequestContext& ctx) {
+        IPC::RequestParser rp{ctx};
+
+        auto mode = static_cast<PerformanceMode>(rp.Pop<u32>());
+        u32 config = rp.Pop<u32>();
+
+        IPC::ResponseBuilder rb{ctx, 2};
+        rb.Push(RESULT_SUCCESS);
+
+        LOG_WARNING(Service_APM, "(STUBBED) called mode=%u config=%u", static_cast<u32>(mode),
+                    config);
+    }
+
+    void GetPerformanceConfiguration(Kernel::HLERequestContext& ctx) {
+        IPC::RequestParser rp{ctx};
+
+        auto mode = static_cast<PerformanceMode>(rp.Pop<u32>());
+
+        IPC::ResponseBuilder rb{ctx, 3};
+        rb.Push(RESULT_SUCCESS);
+        rb.Push<u32>(0); // Performance configuration
+
+        LOG_WARNING(Service_APM, "(STUBBED) called mode=%u", static_cast<u32>(mode));
+    }
+};
+
+APM::APM(std::shared_ptr<Module> apm, const char* name)
+    : ServiceFramework(name), apm(std::move(apm)) {
+    static const FunctionInfo functions[] = {
+        {0, &APM::OpenSession, "OpenSession"},
+        {1, nullptr, "GetPerformanceMode"},
+    };
+    RegisterHandlers(functions);
+}
+
+void APM::OpenSession(Kernel::HLERequestContext& ctx) {
+    IPC::ResponseBuilder rb{ctx, 2, 0, 1};
+    rb.Push(RESULT_SUCCESS);
+    rb.PushIpcInterface<ISession>();
+}
+
+} // namespace APM
+} // namespace Service

src/core/hle/service/apm/interface.h

@@ -0,0 +1,27 @@
+// Copyright 2018 yuzu emulator team
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "core/hle/service/service.h"
+
+namespace Service {
+namespace APM {
+
+class APM final : public ServiceFramework<APM> {
+public:
+    APM(std::shared_ptr<Module> apm, const char* name);
+    ~APM() = default;
+
+private:
+    void OpenSession(Kernel::HLERequestContext& ctx);
+
+    std::shared_ptr<Module> apm;
+};
+
+/// Registers all AM services with the specified service manager.
+void InstallInterfaces(SM::ServiceManager& service_manager);
+
+} // namespace APM
+} // namespace Service

src/core/hle/service/filesystem/fsp_srv.cpp

@@ -70,6 +70,7 @@ private:
 FSP_SRV::FSP_SRV() : ServiceFramework("fsp-srv") {
     static const FunctionInfo functions[] = {
         {1, &FSP_SRV::Initalize, "Initalize"},
+        {18, &FSP_SRV::MountSdCard, "MountSdCard"},
         {200, &FSP_SRV::OpenDataStorageByCurrentProcess, "OpenDataStorageByCurrentProcess"},
         {202, nullptr, "OpenDataStorageByDataId"},
         {203, &FSP_SRV::OpenRomStorage, "OpenRomStorage"},
@@ -96,6 +97,13 @@ void FSP_SRV::Initalize(Kernel::HLERequestContext& ctx) {
     rb.Push(RESULT_SUCCESS);
 }
 
+void FSP_SRV::MountSdCard(Kernel::HLERequestContext& ctx) {
+    LOG_WARNING(Service_FS, "(STUBBED) called");
+
+    IPC::ResponseBuilder rb{ctx, 2};
+    rb.Push(RESULT_SUCCESS);
+}
+
 void FSP_SRV::GetGlobalAccessLogMode(Kernel::HLERequestContext& ctx) {
     LOG_WARNING(Service_FS, "(STUBBED) called");
 

src/core/hle/service/filesystem/fsp_srv.h

@@ -23,6 +23,7 @@ private:
     void TryLoadRomFS();
 
     void Initalize(Kernel::HLERequestContext& ctx);
+    void MountSdCard(Kernel::HLERequestContext& ctx);
     void GetGlobalAccessLogMode(Kernel::HLERequestContext& ctx);
     void OpenDataStorageByCurrentProcess(Kernel::HLERequestContext& ctx);
     void OpenRomStorage(Kernel::HLERequestContext& ctx);

src/core/hle/service/nvdrv/devices/nvhost_as_gpu.cpp

@@ -4,6 +4,7 @@
 
 #include "common/assert.h"
 #include "common/logging/log.h"
+#include "core/core.h"
 #include "core/hle/service/nvdrv/devices/nvhost_as_gpu.h"
 #include "core/hle/service/nvdrv/devices/nvmap.h"
 
@@ -44,11 +45,12 @@ u32 nvhost_as_gpu::AllocateSpace(const std::vector<u8>& input, std::vector<u8>&
     LOG_DEBUG(Service_NVDRV, "called, pages=%x, page_size=%x, flags=%x", params.pages,
               params.page_size, params.flags);
 
+    auto& gpu = Core::System::GetInstance().GPU();
     const u64 size{static_cast<u64>(params.pages) * static_cast<u64>(params.page_size)};
     if (params.flags & 1) {
-        params.offset = memory_manager->AllocateSpace(params.offset, size, 1);
+        params.offset = gpu.memory_manager->AllocateSpace(params.offset, size, 1);
     } else {
-        params.offset = memory_manager->AllocateSpace(size, params.align);
+        params.offset = gpu.memory_manager->AllocateSpace(size, params.align);
     }
 
     std::memcpy(output.data(), &params, output.size());
@@ -71,10 +73,12 @@ u32 nvhost_as_gpu::MapBufferEx(const std::vector<u8>& input, std::vector<u8>& ou
     auto object = nvmap_dev->GetObject(params.nvmap_handle);
     ASSERT(object);
 
+    auto& gpu = Core::System::GetInstance().GPU();
+
     if (params.flags & 1) {
-        params.offset = memory_manager->MapBufferEx(object->addr, params.offset, object->size);
+        params.offset = gpu.memory_manager->MapBufferEx(object->addr, params.offset, object->size);
     } else {
-        params.offset = memory_manager->MapBufferEx(object->addr, object->size);
+        params.offset = gpu.memory_manager->MapBufferEx(object->addr, object->size);
     }
 
     std::memcpy(output.data(), &params, output.size());

src/core/hle/service/nvdrv/devices/nvhost_as_gpu.h

@@ -10,7 +10,6 @@
 #include "common/common_types.h"
 #include "common/swap.h"
 #include "core/hle/service/nvdrv/devices/nvdevice.h"
-#include "core/hle/service/nvdrv/memory_manager.h"
 
 namespace Service {
 namespace Nvidia {
@@ -20,9 +19,7 @@ class nvmap;
 
 class nvhost_as_gpu final : public nvdevice {
 public:
-    nvhost_as_gpu(std::shared_ptr<nvmap> nvmap_dev) : nvdevice(), nvmap_dev(std::move(nvmap_dev)) {
-        memory_manager = std::make_shared<MemoryManager>();
-    }
+    nvhost_as_gpu(std::shared_ptr<nvmap> nvmap_dev) : nvmap_dev(std::move(nvmap_dev)) {}
     ~nvhost_as_gpu() override = default;
 
     u32 ioctl(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;
@@ -101,7 +98,6 @@ private:
     u32 GetVARegions(const std::vector<u8>& input, std::vector<u8>& output);
 
     std::shared_ptr<nvmap> nvmap_dev;
-    std::shared_ptr<MemoryManager> memory_manager;
 };
 
 } // namespace Devices

src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp

@@ -5,6 +5,7 @@
 #include <map>
 #include "common/assert.h"
 #include "common/logging/log.h"
+#include "core/core.h"
 #include "core/hle/service/nvdrv/devices/nvhost_gpu.h"
 
 namespace Service {
@@ -131,7 +132,7 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& outp
                 params.num_entries * sizeof(IoctlGpfifoEntry));
     for (auto entry : entries) {
         VAddr va_addr = entry.Address();
-        // TODO(ogniK): Process these
+        Core::System::GetInstance().GPU().ProcessCommandList(va_addr, entry.sz);
     }
     params.fence_out.id = 0;
     params.fence_out.value = 0;

src/core/hle/service/nvdrv/devices/nvhost_gpu.h

@@ -4,6 +4,7 @@
 
 #pragma once
 
+#include <memory>
 #include <vector>
 #include "common/common_types.h"
 #include "common/swap.h"
@@ -12,12 +13,14 @@
 namespace Service {
 namespace Nvidia {
 namespace Devices {
+
+class nvmap;
 constexpr u32 NVGPU_IOCTL_MAGIC('H');
 constexpr u32 NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO(0x8);
 
 class nvhost_gpu final : public nvdevice {
 public:
-    nvhost_gpu() = default;
+    nvhost_gpu(std::shared_ptr<nvmap> nvmap_dev) : nvmap_dev(std::move(nvmap_dev)) {}
     ~nvhost_gpu() override = default;
 
     u32 ioctl(Ioctl command, const std::vector<u8>& input, std::vector<u8>& output) override;
@@ -132,6 +135,8 @@ private:
     u32 AllocGPFIFOEx2(const std::vector<u8>& input, std::vector<u8>& output);
     u32 AllocateObjectContext(const std::vector<u8>& input, std::vector<u8>& output);
     u32 SubmitGPFIFO(const std::vector<u8>& input, std::vector<u8>& output);
+
+    std::shared_ptr<nvmap> nvmap_dev;
 };
 
 } // namespace Devices

src/core/hle/service/nvdrv/nvdrv.cpp

@@ -32,11 +32,11 @@ void InstallInterfaces(SM::ServiceManager& service_manager) {
 Module::Module() {
     auto nvmap_dev = std::make_shared<Devices::nvmap>();
     devices["/dev/nvhost-as-gpu"] = std::make_shared<Devices::nvhost_as_gpu>(nvmap_dev);
+    devices["/dev/nvhost-gpu"] = std::make_shared<Devices::nvhost_gpu>(nvmap_dev);
     devices["/dev/nvhost-ctrl-gpu"] = std::make_shared<Devices::nvhost_ctrl_gpu>();
     devices["/dev/nvmap"] = nvmap_dev;
     devices["/dev/nvdisp_disp0"] = std::make_shared<Devices::nvdisp_disp0>(nvmap_dev);
     devices["/dev/nvhost-ctrl"] = std::make_shared<Devices::nvhost_ctrl>();
-    devices["/dev/nvhost-gpu"] = std::make_shared<Devices::nvhost_gpu>();
 }
 
 u32 Module::Open(std::string device_name) {

src/core/hle/service/nvflinger/buffer_queue.cpp

@@ -40,7 +40,11 @@ u32 BufferQueue::DequeueBuffer(u32 pixel_format, u32 width, u32 height) {
         return igbp_buffer.format == pixel_format && igbp_buffer.width == width &&
                igbp_buffer.height == height;
     });
-    ASSERT(itr != queue.end());
+    if (itr == queue.end()) {
+        LOG_CRITICAL(Service_NVDRV, "no free buffers for pixel_format=%d, width=%d, height=%d",
+                     pixel_format, width, height);
+        itr = queue.begin();
+    }
 
     itr->status = Buffer::Status::Dequeued;
     return itr->slot;

src/core/hle/service/vi/vi.cpp

@@ -211,7 +211,6 @@ public:
     void DeserializeData() override {
         std::u16string token = ReadInterfaceToken();
         data = Read<Data>();
-        ASSERT(data.graphic_buffer_length == sizeof(NVFlinger::IGBPBuffer));
         buffer = Read<NVFlinger::IGBPBuffer>();
     }
 
@@ -301,14 +300,11 @@ public:
 
 protected:
     void SerializeData() override {
-        // TODO(Subv): Find out what this all means
-        Write<u32_le>(1);
-
-        Write<u32_le>(sizeof(NVFlinger::IGBPBuffer));
-        Write<u32_le>(0); // Unknown
-
+        // TODO(bunnei): Find out what this all means. Writing anything non-zero here breaks libnx.
+        Write<u32_le>(0);
+        Write<u32_le>(0);
+        Write<u32_le>(0);
         Write(buffer);
-
         Write<u32_le>(0);
     }
 
@@ -401,7 +397,7 @@ public:
             {0, &IHOSBinderDriver::TransactParcel, "TransactParcel"},
             {1, &IHOSBinderDriver::AdjustRefcount, "AdjustRefcount"},
             {2, &IHOSBinderDriver::GetNativeHandle, "GetNativeHandle"},
-            {3, nullptr, "TransactParcelAuto"},
+            {3, &IHOSBinderDriver::TransactParcelAuto, "TransactParcelAuto"},
         };
         RegisterHandlers(functions);
     }
@@ -425,35 +421,21 @@ private:
         SetPreallocatedBuffer = 14
     };
 
-    void TransactParcel(Kernel::HLERequestContext& ctx) {
-        IPC::RequestParser rp{ctx};
-        u32 id = rp.Pop<u32>();
-        auto transaction = static_cast<TransactionId>(rp.Pop<u32>());
-        u32 flags = rp.Pop<u32>();
-
-        auto& input_buffer = ctx.BufferDescriptorA()[0];
-        std::vector<u8> input_data(input_buffer.Size());
-        Memory::ReadBlock(input_buffer.Address(), input_data.data(), input_buffer.Size());
-
-        auto& output_buffer = ctx.BufferDescriptorB()[0];
-
+    void TransactParcel(u32 id, TransactionId transaction, const std::vector<u8>& input_data,
+                        VAddr output_addr, u64 output_size) {
         auto buffer_queue = nv_flinger->GetBufferQueue(id);
-        LOG_WARNING(Service_VI, "(STUBBED) called, transaction=%x", transaction);
+        std::vector<u8> response_buffer;
         if (transaction == TransactionId::Connect) {
             IGBPConnectRequestParcel request{input_data};
             IGBPConnectResponseParcel response{1280, 720};
-            auto response_buffer = response.Serialize();
-            Memory::WriteBlock(output_buffer.Address(), response_buffer.data(),
-                               output_buffer.Size());
+            response_buffer = response.Serialize();
         } else if (transaction == TransactionId::SetPreallocatedBuffer) {
             IGBPSetPreallocatedBufferRequestParcel request{input_data};
 
             buffer_queue->SetPreallocatedBuffer(request.data.slot, request.buffer);
 
             IGBPSetPreallocatedBufferResponseParcel response{};
-            auto response_buffer = response.Serialize();
-            Memory::WriteBlock(output_buffer.Address(), response_buffer.data(),
-                               output_buffer.Size());
+            response_buffer = response.Serialize();
         } else if (transaction == TransactionId::DequeueBuffer) {
             IGBPDequeueBufferRequestParcel request{input_data};
 
@@ -461,27 +443,21 @@ private:
                                                    request.data.height);
 
             IGBPDequeueBufferResponseParcel response{slot};
-            auto response_buffer = response.Serialize();
-            Memory::WriteBlock(output_buffer.Address(), response_buffer.data(),
-                               output_buffer.Size());
+            response_buffer = response.Serialize();
         } else if (transaction == TransactionId::RequestBuffer) {
             IGBPRequestBufferRequestParcel request{input_data};
 
             auto& buffer = buffer_queue->RequestBuffer(request.slot);
 
             IGBPRequestBufferResponseParcel response{buffer};
-            auto response_buffer = response.Serialize();
-            Memory::WriteBlock(output_buffer.Address(), response_buffer.data(),
-                               output_buffer.Size());
+            response_buffer = response.Serialize();
         } else if (transaction == TransactionId::QueueBuffer) {
             IGBPQueueBufferRequestParcel request{input_data};
 
             buffer_queue->QueueBuffer(request.data.slot);
 
             IGBPQueueBufferResponseParcel response{1280, 720};
-            auto response_buffer = response.Serialize();
-            Memory::WriteBlock(output_buffer.Address(), response_buffer.data(),
-                               output_buffer.Size());
+            response_buffer = response.Serialize();
         } else if (transaction == TransactionId::Query) {
             IGBPQueryRequestParcel request{input_data};
 
@@ -489,13 +465,47 @@ private:
                 buffer_queue->Query(static_cast<NVFlinger::BufferQueue::QueryType>(request.type));
 
             IGBPQueryResponseParcel response{value};
-            auto response_buffer = response.Serialize();
-            Memory::WriteBlock(output_buffer.Address(), response_buffer.data(),
-                               output_buffer.Size());
+            response_buffer = response.Serialize();
+
         } else {
             ASSERT_MSG(false, "Unimplemented");
         }
 
+        Memory::WriteBlock(output_addr, response_buffer.data(), output_size);
+    }
+
+    void TransactParcel(Kernel::HLERequestContext& ctx) {
+        IPC::RequestParser rp{ctx};
+        u32 id = rp.Pop<u32>();
+        auto transaction = static_cast<TransactionId>(rp.Pop<u32>());
+        u32 flags = rp.Pop<u32>();
+        LOG_DEBUG(Service_VI, "called, transaction=%x", transaction);
+
+        auto& input_buffer = ctx.BufferDescriptorA()[0];
+        auto& output_buffer = ctx.BufferDescriptorB()[0];
+        std::vector<u8> input_data(input_buffer.Size());
+        Memory::ReadBlock(input_buffer.Address(), input_data.data(), input_buffer.Size());
+
+        TransactParcel(id, transaction, input_data, output_buffer.Address(), output_buffer.Size());
+
+        IPC::ResponseBuilder rb{ctx, 2};
+        rb.Push(RESULT_SUCCESS);
+    }
+
+    void TransactParcelAuto(Kernel::HLERequestContext& ctx) {
+        IPC::RequestParser rp{ctx};
+        u32 id = rp.Pop<u32>();
+        auto transaction = static_cast<TransactionId>(rp.Pop<u32>());
+        u32 flags = rp.Pop<u32>();
+        LOG_DEBUG(Service_VI, "called, transaction=%x", transaction);
+
+        auto& input_buffer = ctx.BufferDescriptorX()[0];
+        auto& output_buffer = ctx.BufferDescriptorC()[0];
+        std::vector<u8> input_data(input_buffer.size);
+        Memory::ReadBlock(input_buffer.Address(), input_data.data(), input_buffer.size);
+
+        TransactParcel(id, transaction, input_data, output_buffer.Address(), output_buffer.Size());
+
         IPC::ResponseBuilder rb{ctx, 2};
         rb.Push(RESULT_SUCCESS);
     }

src/video_core/CMakeLists.txt

@@ -1,4 +1,15 @@
 add_library(video_core STATIC
+    command_processor.cpp
+    command_processor.h
+    engines/fermi_2d.cpp
+    engines/fermi_2d.h
+    engines/maxwell_3d.cpp
+    engines/maxwell_3d.h
+    engines/maxwell_compute.cpp
+    engines/maxwell_compute.h
+    gpu.h
+    memory_manager.cpp
+    memory_manager.h
     renderer_base.cpp
     renderer_base.h
     renderer_opengl/gl_resource_manager.h

src/video_core/command_processor.cpp

@@ -0,0 +1,119 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include <array>
+#include <cstddef>
+#include <memory>
+#include <utility>
+#include "common/assert.h"
+#include "common/logging/log.h"
+#include "common/microprofile.h"
+#include "common/vector_math.h"
+#include "core/memory.h"
+#include "core/tracer/recorder.h"
+#include "video_core/command_processor.h"
+#include "video_core/engines/fermi_2d.h"
+#include "video_core/engines/maxwell_3d.h"
+#include "video_core/engines/maxwell_compute.h"
+#include "video_core/gpu.h"
+#include "video_core/renderer_base.h"
+#include "video_core/video_core.h"
+
+namespace Tegra {
+
+enum class BufferMethods {
+    BindObject = 0,
+    CountBufferMethods = 0x100,
+};
+
+void GPU::WriteReg(u32 method, u32 subchannel, u32 value) {
+    LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u value %08X", method, subchannel,
+                value);
+
+    if (method == static_cast<u32>(BufferMethods::BindObject)) {
+        // Bind the current subchannel to the desired engine id.
+        LOG_DEBUG(HW_GPU, "Binding subchannel %u to engine %u", subchannel, value);
+        ASSERT(bound_engines.find(subchannel) == bound_engines.end());
+        bound_engines[subchannel] = static_cast<EngineID>(value);
+        return;
+    }
+
+    if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
+        // TODO(Subv): Research and implement these methods.
+        LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
+        return;
+    }
+
+    ASSERT(bound_engines.find(subchannel) != bound_engines.end());
+
+    const EngineID engine = bound_engines[subchannel];
+
+    switch (engine) {
+    case EngineID::FERMI_TWOD_A:
+        fermi_2d->WriteReg(method, value);
+        break;
+    case EngineID::MAXWELL_B:
+        maxwell_3d->WriteReg(method, value);
+        break;
+    case EngineID::MAXWELL_COMPUTE_B:
+        maxwell_compute->WriteReg(method, value);
+        break;
+    default:
+        UNIMPLEMENTED();
+    }
+}
+
+void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
+    // TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
+    // application VAddr.
+    const VAddr head_address = memory_manager->PhysicalToVirtualAddress(address);
+    VAddr current_addr = head_address;
+    while (current_addr < head_address + size * sizeof(CommandHeader)) {
+        const CommandHeader header = {Memory::Read32(current_addr)};
+        current_addr += sizeof(u32);
+
+        switch (header.mode.Value()) {
+        case SubmissionMode::IncreasingOld:
+        case SubmissionMode::Increasing: {
+            // Increase the method value with each argument.
+            for (unsigned i = 0; i < header.arg_count; ++i) {
+                WriteReg(header.method + i, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::NonIncreasingOld:
+        case SubmissionMode::NonIncreasing: {
+            // Use the same method value for all arguments.
+            for (unsigned i = 0; i < header.arg_count; ++i) {
+                WriteReg(header.method, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::IncreaseOnce: {
+            ASSERT(header.arg_count.Value() >= 1);
+            // Use the original method for the first argument and then the next method for all other
+            // arguments.
+            WriteReg(header.method, header.subchannel, Memory::Read32(current_addr));
+            current_addr += sizeof(u32);
+            // Use the same method value for all arguments.
+            for (unsigned i = 1; i < header.arg_count; ++i) {
+                WriteReg(header.method + 1, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::Inline: {
+            // The register value is stored in the bits 16-28 as an immediate
+            WriteReg(header.method, header.subchannel, header.inline_data);
+            break;
+        }
+        default:
+            UNIMPLEMENTED();
+        }
+    }
+}
+
+} // namespace Tegra

src/video_core/command_processor.h

@@ -0,0 +1,39 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <type_traits>
+#include "common/bit_field.h"
+#include "common/common_types.h"
+
+namespace Tegra {
+
+enum class SubmissionMode : u32 {
+    IncreasingOld = 0,
+    Increasing = 1,
+    NonIncreasingOld = 2,
+    NonIncreasing = 3,
+    Inline = 4,
+    IncreaseOnce = 5
+};
+
+union CommandHeader {
+    u32 hex;
+
+    BitField<0, 13, u32> method;
+    BitField<13, 3, u32> subchannel;
+
+    BitField<16, 13, u32> arg_count;
+    BitField<16, 13, u32> inline_data;
+
+    BitField<29, 3, SubmissionMode> mode;
+};
+static_assert(std::is_standard_layout<CommandHeader>::value == true,
+              "CommandHeader does not use standard layout");
+static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect size!");
+
+void ProcessCommandList(VAddr address, u32 size);
+
+} // namespace Tegra

src/video_core/engines/fermi_2d.cpp

@@ -0,0 +1,13 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "video_core/engines/fermi_2d.h"
+
+namespace Tegra {
+namespace Engines {
+
+void Fermi2D::WriteReg(u32 method, u32 value) {}
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/fermi_2d.h

@@ -0,0 +1,22 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+namespace Tegra {
+namespace Engines {
+
+class Fermi2D final {
+public:
+    Fermi2D() = default;
+    ~Fermi2D() = default;
+
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+};
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_3d.cpp

@@ -0,0 +1,51 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/assert.h"
+#include "video_core/engines/maxwell_3d.h"
+
+namespace Tegra {
+namespace Engines {
+
+Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
+
+void Maxwell3D::WriteReg(u32 method, u32 value) {
+    ASSERT_MSG(method < Regs::NUM_REGS,
+               "Invalid Maxwell3D register, increase the size of the Regs structure");
+
+    regs.reg_array[method] = value;
+
+#define MAXWELL3D_REG_INDEX(field_name) (offsetof(Regs, field_name) / sizeof(u32))
+
+    switch (method) {
+    case MAXWELL3D_REG_INDEX(query.query_get): {
+        ProcessQueryGet();
+        break;
+    }
+    default:
+        break;
+    }
+
+#undef MAXWELL3D_REG_INDEX
+}
+
+void Maxwell3D::ProcessQueryGet() {
+    GPUVAddr sequence_address = regs.query.QueryAddress();
+    // Since the sequence address is given as a GPU VAddr, we have to convert it to an application
+    // VAddr before writing.
+    VAddr address = memory_manager.PhysicalToVirtualAddress(sequence_address);
+
+    switch (regs.query.query_get.mode) {
+    case Regs::QueryMode::Write: {
+        // Write the current query sequence to the sequence address.
+        u32 sequence = regs.query.query_sequence;
+        Memory::Write32(address, sequence);
+        break;
+    }
+    default:
+        UNIMPLEMENTED_MSG("Query mode %u not implemented", regs.query.query_get.mode.Value());
+    }
+}
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_3d.h

@@ -0,0 +1,76 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/bit_field.h"
+#include "common/common_funcs.h"
+#include "common/common_types.h"
+#include "video_core/memory_manager.h"
+
+namespace Tegra {
+namespace Engines {
+
+class Maxwell3D final {
+public:
+    Maxwell3D(MemoryManager& memory_manager);
+    ~Maxwell3D() = default;
+
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+
+    /// Register structure of the Maxwell3D engine.
+    /// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
+    struct Regs {
+        static constexpr size_t NUM_REGS = 0xE36;
+
+        enum class QueryMode : u32 {
+            Write = 0,
+            Sync = 1,
+        };
+
+        union {
+            struct {
+                INSERT_PADDING_WORDS(0x6C0);
+                struct {
+                    u32 query_address_high;
+                    u32 query_address_low;
+                    u32 query_sequence;
+                    union {
+                        u32 raw;
+                        BitField<0, 2, QueryMode> mode;
+                        BitField<4, 1, u32> fence;
+                        BitField<12, 4, u32> unit;
+                    } query_get;
+
+                    GPUVAddr QueryAddress() const {
+                        return static_cast<GPUVAddr>(
+                            (static_cast<GPUVAddr>(query_address_high) << 32) | query_address_low);
+                    }
+                } query;
+                INSERT_PADDING_WORDS(0x772);
+            };
+            std::array<u32, NUM_REGS> reg_array;
+        };
+    } regs{};
+
+    static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
+
+private:
+    /// Handles a write to the QUERY_GET register.
+    void ProcessQueryGet();
+
+    MemoryManager& memory_manager;
+};
+
+#define ASSERT_REG_POSITION(field_name, position)                                                  \
+    static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4,                           \
+                  "Field " #field_name " has invalid position")
+
+ASSERT_REG_POSITION(query, 0x6C0);
+
+#undef ASSERT_REG_POSITION
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_compute.cpp

@@ -0,0 +1,13 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "video_core/engines/maxwell_compute.h"
+
+namespace Tegra {
+namespace Engines {
+
+void MaxwellCompute::WriteReg(u32 method, u32 value) {}
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_compute.h

@@ -0,0 +1,22 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+namespace Tegra {
+namespace Engines {
+
+class MaxwellCompute final {
+public:
+    MaxwellCompute() = default;
+    ~MaxwellCompute() = default;
+
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+};
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/gpu.h

@@ -0,0 +1,55 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <memory>
+#include <unordered_map>
+#include "common/common_types.h"
+#include "video_core/engines/fermi_2d.h"
+#include "video_core/engines/maxwell_3d.h"
+#include "video_core/engines/maxwell_compute.h"
+#include "video_core/memory_manager.h"
+
+namespace Tegra {
+
+enum class EngineID {
+    FERMI_TWOD_A = 0x902D, // 2D Engine
+    MAXWELL_B = 0xB197,    // 3D Engine
+    MAXWELL_COMPUTE_B = 0xB1C0,
+    KEPLER_INLINE_TO_MEMORY_B = 0xA140,
+    MAXWELL_DMA_COPY_A = 0xB0B5,
+};
+
+class GPU final {
+public:
+    GPU() {
+        memory_manager = std::make_unique<MemoryManager>();
+        maxwell_3d = std::make_unique<Engines::Maxwell3D>(*memory_manager);
+        fermi_2d = std::make_unique<Engines::Fermi2D>();
+        maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
+    }
+    ~GPU() = default;
+
+    /// Processes a command list stored at the specified address in GPU memory.
+    void ProcessCommandList(GPUVAddr address, u32 size);
+
+    std::unique_ptr<MemoryManager> memory_manager;
+
+private:
+    /// Writes a single register in the engine bound to the specified subchannel
+    void WriteReg(u32 method, u32 subchannel, u32 value);
+
+    /// Mapping of command subchannels to their bound engine ids.
+    std::unordered_map<u32, EngineID> bound_engines;
+
+    /// 3D engine
+    std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
+    /// 2D engine
+    std::unique_ptr<Engines::Fermi2D> fermi_2d;
+    /// Compute engine
+    std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
+};
+
+} // namespace Tegra

src/video_core/memory_manager.cpp

@@ -3,10 +3,9 @@
 // Refer to the license.txt file included.
 
 #include "common/assert.h"
-#include "core/hle/service/nvdrv/memory_manager.h"
+#include "video_core/memory_manager.h"
 
-namespace Service {
-namespace Nvidia {
+namespace Tegra {
 
 PAddr MemoryManager::AllocateSpace(u64 size, u64 align) {
     boost::optional<PAddr> paddr = FindFreeBlock(size, align);
@@ -108,5 +107,4 @@ VAddr& MemoryManager::PageSlot(PAddr paddr) {
     return (*block)[(paddr >> Memory::PAGE_BITS) & PAGE_BLOCK_MASK];
 }
 
-} // namespace Nvidia
-} // namespace Service
+} // namespace Tegra

src/video_core/memory_manager.h

@@ -9,8 +9,10 @@
 #include "common/common_types.h"
 #include "core/memory.h"
 
-namespace Service {
-namespace Nvidia {
+namespace Tegra {
+
+/// Virtual addresses in the GPU's memory map are 64 bit.
+using GPUVAddr = u64;
 
 class MemoryManager final {
 public:
@@ -44,5 +46,4 @@ private:
     std::array<std::unique_ptr<PageBlock>, PAGE_TABLE_SIZE> page_table{};
 };
 
-} // namespace Nvidia
-} // namespace Service
+} // namespace Tegra