gl_shader_decompiler: Implement TEXS.F16

src/core/file_sys/system_archive/ng_word.cpp

@@ -26,7 +26,7 @@ constexpr std::array<u8, 30> WORD_TXT{
 VirtualDir NgWord1() {
     std::vector<VirtualFile> files(NgWord1Data::NUMBER_WORD_TXT_FILES);
 
-    for (std::size_t i = 0; i < files.size(); ++i) {
+    for (std::size_t i = 0; i < NgWord1Data::NUMBER_WORD_TXT_FILES; ++i) {
         files[i] = std::make_shared<ArrayVfsFile<NgWord1Data::WORD_TXT.size()>>(
             NgWord1Data::WORD_TXT, fmt::format("{}.txt", i));
     }

src/core/file_sys/system_archive/system_archive.cpp

@@ -2,6 +2,7 @@
 // Licensed under GPLv2 or any later version
 // Refer to the license.txt file included.
 
+#include <functional>
 #include "common/logging/log.h"
 #include "core/file_sys/romfs.h"
 #include "core/file_sys/system_archive/ng_word.h"
@@ -12,7 +13,7 @@ namespace FileSys::SystemArchive {
 constexpr u64 SYSTEM_ARCHIVE_BASE_TITLE_ID = 0x0100000000000800;
 constexpr std::size_t SYSTEM_ARCHIVE_COUNT = 0x28;
 
-using SystemArchiveSupplier = VirtualDir (*)();
+using SystemArchiveSupplier = std::function<VirtualDir()>;
 
 struct SystemArchiveDescriptor {
     u64 title_id;
@@ -20,7 +21,7 @@ struct SystemArchiveDescriptor {
     SystemArchiveSupplier supplier;
 };
 
-constexpr std::array<SystemArchiveDescriptor, SYSTEM_ARCHIVE_COUNT> SYSTEM_ARCHIVES{{
+const std::array<SystemArchiveDescriptor, SYSTEM_ARCHIVE_COUNT> SYSTEM_ARCHIVES = {{
     {0x0100000000000800, "CertStore", nullptr},
     {0x0100000000000801, "ErrorMessage", nullptr},
     {0x0100000000000802, "MiiModel", nullptr},

src/core/hle/service/filesystem/fsp_srv.cpp

@@ -796,18 +796,9 @@ void FSP_SRV::OpenSaveDataInfoReaderBySaveDataSpaceId(Kernel::HLERequestContext&
 void FSP_SRV::GetGlobalAccessLogMode(Kernel::HLERequestContext& ctx) {
     LOG_WARNING(Service_FS, "(STUBBED) called");
 
-    enum class LogMode : u32 {
-        Off,
-        Log,
-        RedirectToSdCard,
-        LogToSdCard = Log | RedirectToSdCard,
-    };
-
-    // Given we always want to receive logging information,
-    // we always specify logging as enabled.
     IPC::ResponseBuilder rb{ctx, 3};
     rb.Push(RESULT_SUCCESS);
-    rb.PushEnum(LogMode::Log);
+    rb.Push<u32>(5);
 }
 
 void FSP_SRV::OpenDataStorageByCurrentProcess(Kernel::HLERequestContext& ctx) {

src/core/hle/service/ldr/ldr.cpp

@@ -335,7 +335,10 @@ public:
         vm_manager.ReprotectRange(*map_address + header.rw_offset, header.rw_size,
                                   Kernel::VMAPermission::ReadWrite);
 
-        Core::System::GetInstance().InvalidateCpuInstructionCaches();
+        Core::System::GetInstance().ArmInterface(0).ClearInstructionCache();
+        Core::System::GetInstance().ArmInterface(1).ClearInstructionCache();
+        Core::System::GetInstance().ArmInterface(2).ClearInstructionCache();
+        Core::System::GetInstance().ArmInterface(3).ClearInstructionCache();
 
         nro.insert_or_assign(*map_address, NROInfo{hash, nro_size + bss_size});
 
@@ -388,7 +391,10 @@ public:
                                      Kernel::MemoryState::ModuleCodeStatic) == RESULT_SUCCESS);
         ASSERT(process->UnmapMemory(mapped_addr, 0, nro_size) == RESULT_SUCCESS);
 
-        Core::System::GetInstance().InvalidateCpuInstructionCaches();
+        Core::System::GetInstance().ArmInterface(0).ClearInstructionCache();
+        Core::System::GetInstance().ArmInterface(1).ClearInstructionCache();
+        Core::System::GetInstance().ArmInterface(2).ClearInstructionCache();
+        Core::System::GetInstance().ArmInterface(3).ClearInstructionCache();
 
         nro.erase(iter);
         IPC::ResponseBuilder rb{ctx, 2};

src/core/memory.cpp

@@ -53,14 +53,6 @@ void PageTable::Resize(std::size_t address_space_width_in_bits) {
 
     pointers.resize(num_page_table_entries);
     attributes.resize(num_page_table_entries);
-
-    // The default is a 39-bit address space, which causes an initial 1GB allocation size. If the
-    // vector size is subsequently decreased (via resize), the vector might not automatically
-    // actually reallocate/resize its underlying allocation, which wastes up to ~800 MB for
-    // 36-bit titles. Call shrink_to_fit to reduce capacity to what's actually in use.
-
-    pointers.shrink_to_fit();
-    attributes.shrink_to_fit();
 }
 
 static void MapPages(PageTable& page_table, VAddr base, u64 size, u8* memory, PageType type) {

src/video_core/engines/shader_bytecode.h

@@ -1049,6 +1049,7 @@ union Instruction {
         BitField<49, 1, u64> nodep_flag;
         BitField<50, 3, u64> component_mask_selector;
         BitField<53, 4, u64> texture_info;
+        BitField<60, 1, u64> fp32_flag;
 
         TextureType GetTextureType() const {
             // The TEXS instruction has a weird encoding for the texture type.
@@ -1549,7 +1550,7 @@ private:
             INST("1110111011011---", Id::STG, Type::Memory, "STG"),
             INST("110000----111---", Id::TEX, Type::Memory, "TEX"),
             INST("1101111101001---", Id::TXQ, Type::Memory, "TXQ"),
-            INST("1101100---------", Id::TEXS, Type::Memory, "TEXS"),
+            INST("1101-00---------", Id::TEXS, Type::Memory, "TEXS"),
             INST("1101101---------", Id::TLDS, Type::Memory, "TLDS"),
             INST("110010----111---", Id::TLD4, Type::Memory, "TLD4"),
             INST("1101111100------", Id::TLD4S, Type::Memory, "TLD4S"),

src/video_core/renderer_opengl/gl_shader_decompiler.cpp

@@ -50,6 +50,14 @@ public:
     using std::runtime_error::runtime_error;
 };
 
+/// Generates code to use for a swizzle operation.
+static std::string GetSwizzle(u64 elem) {
+    ASSERT(elem <= 3);
+    std::string swizzle = ".";
+    swizzle += "xyzw"[elem];
+    return swizzle;
+}
+
 /// Translate topology
 static std::string GetTopologyName(Tegra::Shader::OutputTopology topology) {
     switch (topology) {
@@ -1004,14 +1012,6 @@ private:
         }
     }
 
-    /// Generates code to use for a swizzle operation.
-    static std::string GetSwizzle(u64 elem) {
-        ASSERT(elem <= 3);
-        std::string swizzle = ".";
-        swizzle += "xyzw"[elem];
-        return swizzle;
-    }
-
     ShaderWriter& shader;
     ShaderWriter& declarations;
     std::vector<GLSLRegister> regs;
@@ -1343,7 +1343,7 @@ private:
         regs.SetRegisterToInteger(dest, true, 0, result, 1, 1);
     }
 
-    void WriteTexsInstruction(const Instruction& instr, const std::string& texture) {
+    void WriteTexsInstructionFloat(const Instruction& instr, const std::string& texture) {
         // TEXS has two destination registers and a swizzle. The first two elements in the swizzle
         // go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1
 
@@ -1368,6 +1368,38 @@ private:
         }
     }
 
+    void WriteTexsInstructionHalfFloat(const Instruction& instr, const std::string& texture) {
+        // TEXS.F16 destionation registers are packed in two registers in pairs (just like any half
+        // float instruction).
+
+        std::array<std::string, 4> components;
+        u32 written_components = 0;
+
+        for (u32 component = 0; component < 4; ++component) {
+            if (!instr.texs.IsComponentEnabled(component))
+                continue;
+            components[written_components++] = texture + GetSwizzle(component);
+        }
+        if (written_components == 0)
+            return;
+
+        const auto BuildComponent = [&](std::string low, std::string high, bool high_enabled) {
+            return "vec2(" + low + ", " + (high_enabled ? high : "0") + ')';
+        };
+
+        regs.SetRegisterToHalfFloat(
+            instr.gpr0, 0, BuildComponent(components[0], components[1], written_components > 1),
+            Tegra::Shader::HalfMerge::H0_H1, 1, 1);
+
+        if (written_components > 2) {
+            ASSERT(instr.texs.HasTwoDestinations());
+            regs.SetRegisterToHalfFloat(
+                instr.gpr28, 0,
+                BuildComponent(components[2], components[3], written_components > 3),
+                Tegra::Shader::HalfMerge::H0_H1, 1, 1);
+        }
+    }
+
     static u32 TextureCoordinates(Tegra::Shader::TextureType texture_type) {
         switch (texture_type) {
         case Tegra::Shader::TextureType::Texture1D:
@@ -2766,24 +2798,27 @@ private:
                 const bool depth_compare =
                     instr.texs.UsesMiscMode(Tegra::Shader::TextureMiscMode::DC);
                 const auto process_mode = instr.texs.GetTextureProcessMode();
+
                 UNIMPLEMENTED_IF_MSG(instr.texs.UsesMiscMode(Tegra::Shader::TextureMiscMode::NODEP),
                                      "NODEP is not implemented");
 
                 const auto scope = shader.Scope();
 
-                const auto [coord, texture] =
+                auto [coord, texture] =
                     GetTEXSCode(instr, texture_type, process_mode, depth_compare, is_array);
 
                 shader.AddLine(coord);
 
-                if (!depth_compare) {
-                    shader.AddLine("vec4 texture_tmp = " + texture + ';');
-
-                } else {
-                    shader.AddLine("vec4 texture_tmp = vec4(" + texture + ");");
+                if (depth_compare) {
+                    texture = "vec4(" + texture + ')';
                 }
+                shader.AddLine("vec4 texture_tmp = " + texture + ';');
 
-                WriteTexsInstruction(instr, "texture_tmp");
+                if (instr.texs.fp32_flag) {
+                    WriteTexsInstructionFloat(instr, "texture_tmp");
+                } else {
+                    WriteTexsInstructionHalfFloat(instr, "texture_tmp");
+                }
                 break;
             }
             case OpCode::Id::TLDS: {
@@ -2842,7 +2877,7 @@ private:
                     }
                 }();
 
-                WriteTexsInstruction(instr, texture);
+                WriteTexsInstructionFloat(instr, texture);
                 break;
             }
             case OpCode::Id::TLD4: {
@@ -2940,7 +2975,8 @@ private:
                 if (depth_compare) {
                     texture = "vec4(" + texture + ')';
                 }
-                WriteTexsInstruction(instr, texture);
+
+                WriteTexsInstructionFloat(instr, texture);
                 break;
             }
             case OpCode::Id::TXQ: {